Spin-transfer torque magnetoresistive random access memories (STT-MRAM) are nonvolatile memories that store changeable bit data values in the relative orientations of magnetic fields in one or more magnetic terminal junction (MTJ) elements that comprise a fixed magnetic layer and a changeable magnetic layer, separated by a nonmagnetic conductive barrier.
A binary data value is represented in an MTJ element, by orienting the changeable magnetic layer parallel to the fixed magnetic layer, which is a low resistance state, or anti-parallel, which is a high resistance state. For reading out the stored bit data value, the serial resistance through the layers is detected by comparison with a threshold value, typically comparing a current or voltage parameter that varies with resistance, versus a threshold of current or voltage representing a resistance between the high and low resistance states.
When writing a data value to an MTJ element, a write bias current of a particular current polarity, and at least a minimum amplitude, is passed through the element. Opposite polarity write currents are necessary to impose opposite data values represented by the high and low resistance states. When reading out the stored value in the MTJ element (i.e., when detecting its resistance state), the current or voltage coupled to the element for producing a voltage or current, respectively, according to Ohm's Law V=IR must be at one polarity or the other. Therefore, there is a potential that some combinations of a present resistance state and a particular read current polarity may inadvertently change the state of the MTJ element during a read operation. This is known as a read disturb error.
A memory circuit containing MTJ elements typically has numerous addressable data words having bit positions, each word and bit position having an associated MTJ element that can be coupled to a sense amplifier operating as a comparator, to read out the data value of that bit. Inasmuch as the high and low resistance values of the numerous MTJ elements are distributed over a range, a problem is encountered in defining the best threshold value to use when attempting to discern whether the MTJ element is in its high or low resistance state. In some possible methods for discriminating for resistance using comparison thresholds, the chosen threshold may fall outside the span between the high resistance RH and low resistance RL of some of the MTJ elements, making those bits defective even though the MTJ elements are operational to assume distinct resistance states. According to product selection criteria, at some number of defective bits (possibly only one bit), the memory circuit may be considered defective.
Instead of seeking to specify a fixed resistance (or related voltage or current parameter) for as a comparison threshold, two or more MTJ elements can be associated together as one bit cell with plural MTJ elements. Assuming two MTJ elements, one of the two MTJ elements is kept in a high resistance state when the other is in a low resistance state. The binary data value stored by the bit cell is defined by which of the two is in the high resistance state and which is in the low resistance state.
Writing any value to a two-MTJ bit cell requires the application of write currents of opposite polarity to the two MTJ elements of the bit cell, respectively. The particular logic value that is written depends on the sense of the opposite polarities, such as positive/negative to write a binary one and negative/positive write a binary zero. The two logic values are represented by high/low or low/high resistance states in the two MTJ elements.
It is useful to have two MTJ elements in one bit cell because the resistances of the two (or a resistance related parameter such as voltage or current) can be compared against one another instead of being compared against an external reference. But developing parameter values that can be compared requires the application of current bias and the bias is necessarily at one polarity or another. The logic value stored in a bit cell is arbitrary and unknown until it is read out. The two MTJ elements are maintained in opposite resistance states, regardless of logic value. There seems to be an inherent risk of read-disturb errors and a need to limit the amplitude of read current bias for all bit cells to an amplitude that will not disturb the resistance state of the most sensitive MTJ element in the memory array.
Techniques are needed to optimize operation of plural MTJ elements used in sets of two or more complementary elements forming a bit cell. Such techniques should optimize the balance between the selection rate of MTJ elements (considering that their high and low resistance values vary over a statistical distribution) versus the need to conserve circuit area (given that two MTJ elements occupy twice the area of one MTJ element). Such techniques should also take into account that the need for opposite polarity read and write current bias and the need to switch that opposite polarity back and forth as function of logic level, require that some of the circuit area be devoted to switching devices as opposed to MTJ elements for nonvolatile storage of information in a changeable resistance.